Staff EDA Engineer at Lattice Semiconductor in Pune

Job description

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Job Description: Lattice is seeking a Senior CAD/EDA Engineer with deep expertise in Static Timing Analysis (STA), Place and Route (PNR), and hierarchical timing abstraction using Extracted Timing Models (ETM) and Quick Timing Models (QTM), to join our CAD/EDA Engineering group in Pune, India. Qualified candidates must hold a BS or MS degree in EE, ECE, or CoE with 8 to 12 years of industry experience on 5, 7, 16, or 28 nm process technology nodes. This individual will be a key driver in developing, deploying, and supporting the logic and digital design implementation and signoff methodologies and flows across the company's FPGA product lines The candidate's general responsibilities include the following: Static Timing Analysis and Signoff Own and maintain the multi-corner multi-mode (MCMM) STA signoff methodology, including constraint development, timing closure criteria, and signoff sign-check automation. Develop and support timing signoff flows using Synopsys PrimeTime, PrimeTime SI, and Cadence Tempus, covering setup, hold, recovery/removal, and transition/capacitance checks. Deploy advanced variation modeling methodologies including AOCV, POCV, and LVF, and define derating and margining strategies across process nodes. Drive crosstalk and signal integrity analysis, noise-aware timing, and correlation between implementation and signoff timing engines. Define and automate SDC generation, validation, and equivalence checking across RTL, synthesis, PNR, and signoff stages. Timing Abstraction: ETM and QTM Own the hierarchical timing model generation methodology, including ETM extraction for hardened blocks and IP, and QTM construction for blocks that are not yet implemented. Define model validation and correlation procedures that quantify ETM/QTM accuracy against flat and full block timing, and establish acceptance criteria for model release. Develop automation for context-aware and mode-aware model generation, interface logic model (ILM) alternatives, and model regeneration triggered by block-level ECOs. Drive top-level timing closure strategies that rely on abstracted models to reduce runtime and memory footprint on large hierarchical designs. Establish guidance for design teams on when to apply ETM, QTM, ILM, or flat analysis, and document the accuracy and runtime trade-offs of each. Physical Implementation and Place and Route Develop and support physical design place and route and tape-out flows for advanced FinFET nodes (28nm, 16nm, 7 nm and below) using Cadence Innovus and/or Synopsys IC Compiler II and Fusion Compiler. Drive floorplanning, power planning, placement, clock tree synthesis, and routing methodology, including low-skew and clock mesh structures. Own post-CTS and post-route tool ECO flows, timing and DRV closure automation, and physical-aware ECO implementation. Support early IR drop and power analysis, EM/IR signoff hooks, and congestion and routability analysis within the implementation flow. Support IP block and full-chip integration for designs on 5, 7, 16, and 28 nm process nodes. Methodology, Au