Senior Staff Digital Methodology Engineer - Design for Testability (DFT) at Synopsys in Bengaluru

Job description

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Job Description and Requirements We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent over a decade architecting test solutions for chips that power everything from autonomous vehicles to data centers, and you understand that DFT is not an afterthought, it is the difference between a design that ships on time and one that bleeds money in yield loss. You know the nuances of scan compression versus hierarchical DFT, not from a textbook, but from making the call on a 10-billion-gate SoC where the wrong decision costs months. You are the person design teams call when ATPG coverage is stuck at 97% and manufacturing is demanding 99.5%. You have debugged IJTAG networks that span multiple chiplets, written the Tcl that automated what used to take three engineers a week, and sat in rooms with VPs explaining why their test access strategy needs to change before tapeout. You do not just know the IEEE standards, you have deployed them in production silicon and lived with the consequences. At Synopsys, you will work on methodologies that define how the world's most complex chips get tested. The problems are hard, the customers are sophisticated, and what you build will matter. What You'll Be Doing Define and drive DFT methodologies for next-generation ASIC and SoC designs across strategic customer programs, translating architecture decisions into deployable best practices Lead deployment of advanced test solutions including scan compression, hierarchical DFT, IEEE 1500 wrappers, IJTAG instrumentation networks, and embedded test IP across multi-billion-gate designs Architect scalable test access infrastructures using IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500 standards for complex multi-die and chiplet-based systems Develop automation frameworks, signoff criteria, and reusable methodology packages using Tcl, Python, and Perl that accelerate adoption across business units Serve as technical leader and subject matter expert for Synopsys TestMAX DFT, TestMAX ATPG, diagnosis, and silicon lifecycle solutions in customer engagements and internal escalations Collaborate directly with R&D teams to influence TestMAX product roadmap based on real deployment challenges and customer requirements Provide technical leadership for strategic customer engagements, methodology reviews, and complex DFT architecture decisions that impact tapeout schedules and silicon success The Impact You Will Have Enable successful deployment of industry-leading DFT methodologies across the world's most advanced semiconductor programs in AI, automotive, and hyperscale computing Drive measurable improvements in test coverage, pattern count reduction, and manufacturing yield through methodology standardization and best-practice development Influence next-generation TestMAX capabilities by translating customer deployment challenges into product requirements that shape future releases Accelerate adoption of standards-based test architectures across strategic accounts, reducing time-to-market and improving silicon reliability Improve engineering productivity across multiple programs through automation frameworks and reusable methodology packages that eliminate redundant work Establish Synopsys as the trusted technical advisor in DFT and manufacturing test, strengthening customer relationships