Senior Layout Design Engineer at Synopsys in Noida

Job description

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Job Description and Requirements Layout Design, Sr Engineer We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years translating analog circuit schematics into physical layouts that actually perform, not just pass DRC. You know that a GPIO layout is not just about routing metal, it is about understanding how a 2pF mismatch or a 10-micron shift can break ESD performance or skew I/O timing in ways the schematic never predicted. You think in cross-sections and current density maps, and you have learned to spot a latchup risk or a substrate coupling problem before it ever hits silicon. You are comfortable sitting with a circuit designer who hands you a half-finished schematic and a set of constraints, and you know which questions to ask to turn that into a layout that meets area, performance, and reliability targets. Matching does not scare you, it is something you have done enough times to have opinions about dummy placement and orientation strategies. You have debugged parasitic extraction results at 2 a.m. and lived to tell the story. Automation is not a nice-to-have for you, it is how you stay sane. You write scripts to check spacing rules, generate array structures, or pull reports because doing it manually fifteen times is not an option. At Synopsys, you will work on IO and analog IP that ships in real products, with a team that knows the difference between a layout that works and one that just closes. What You'll Be Doing Design and own full custom analog layouts for GPIO, specialty IO, and general-purpose analog IP blocks including I2C, I3C, SMBUS, eMMC, SVID, Quad SPI, and JTAG interfaces Develop high-performance LVDS layouts and crystal oscillator circuits with attention to signal integrity, noise coupling, and parasitic management Collaborate with circuit designers to translate schematics into physical implementations that meet area, performance, matching, and reliability specifications Perform layout verification including DRC, LVS, and parasitic extraction analysis, iterating with design teams to close on performance targets Build and maintain layout automation scripts to improve design efficiency, consistency, and quality across IP families Provide technical guidance and layout reviews for junior engineers, helping them develop skills in analog matching, IO frame design, and technology-specific layout techniques Work across global teams in the US, Europe, and Asia to align on design standards, schedules, and deliverables for multi-site IP development programs The Impact You Will Have Your layouts will directly enable GPIO and specialty IO performance in Synopsys IP that powers AI, automotive, and high-performance computing chips used by leading semiconductor companies You will help reduce design cycle time and improve first-pass silicon success rates through high-quality layout and proactive parasitic management The automation scripts and layout methodologies you develop will become reusable assets across multiple IP families and process nodes Your technical reviews and mentorship will raise the skill level of the layout team and reduce costly respins caused by layout-induced performance issues You will contribute to IP roadmaps by identifying layout-driven design constraints early, influencing architecture decisions before they become