Senior Design Verification Engineer (IP) at Lattice Semiconductor in Penang

Job description

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Job Description: Job Summary: There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation and customer service, and to that focus we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Lattice Semiconductor is seeking a senior Design Verification Engineer to join the RnD organization. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow. Responsibilities & Skills: We are seeking a Senior IP DV engineer with significant hands-on experience in pre-silicon Design verification, verification methodologies and UVM. Develop and Review Comprehensive Test Plan based on design specification Develop, and maintain scalable UVM-based constrained-random verification environments for complex IPs Create test cases, sequences, scoreboards, checkers, and assertions based on testplan and drive verification execution from planning through coverage closure and sign-off. Analyze failures and perform root-cause debugging of design and verification issues. Collaborate closely with design, architecture, system validation, and application teams to resolve functional and performance issues and customer escapes. Contribute to verification methodology improvements, automation initiatives, and best practices across the team. Requirements: Good understanding of verification process from test plan through coverage closure and sign-off Hands-on experience with SystemVerilog and UVM verification methodologies. Experience developing constrained-random verification environments for complex digital designs. Strong debugging, analytical, and problem-solving skills. Excellent communication and teamwork skills in a cross-functional and geographically distributed environment. Strong communication and Analytical skills Good understanding of HDL (Verilog, SystemVerilog) Experience with designing with FPGA is a plus Proficiency in at least one scripting or programming language such as Python, Tcl, Perl, or C/C++. Experience in one or more of the following areas is highly desirable: High speed Interface Protocols (Ethernet, PCIe, CPRI or JESD204B/C, USB), Memory (DRAM, SRAM, Flash, DMA), Interconnect (AMBA AXI, AHB, APB), Peripherals (SPI, I2C or I3C) Education and General: BS/MS/PhD in Electrical Engineering, Electronics Engineering, Computer Engineering Minimum 5+ y