Senior Design Engineer - Modeling at Lattice Semiconductor in Manila

Job description

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Job Description: This position for Senior Design Engineer - Modeling builds and runs the stand-alone testbenches, tests, regressions, and equivalence flows that independently validate the behavioral, functional, and architectural models and related collateral delivered by the Design Modeling team. The role ensures that delivered models, especially those used for user and software simulations, are functionally correct and equivalent to the actual hardware design. The engineer works as part of the new Unit Testing team under the direction of the Design Modeling Manager and the Staff Design Engineer, and collaborates closely with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams. The position supports validation of HLM, XML, and generated Chip Builder artifacts, enabling the senior modeling engineers to remain focused on customer commitments and delivery. Key Responsibilities Develop stand-alone testbenches, directed and constrained-random tests, checkers, and scoreboards, in UVM or non-UVM format, to verify that functional and behavioral models match the actual hardware design. Build regression suites, coverage collection, and coverage dashboards, and support release qualification of HLM, IP XML, and generated Chip Builder artifacts against measurable release-exit criteria. Author, maintain, and execute test plans for assigned behavioral, functional, and architectural models, tracing each feature and behavior to tests and coverage points. Execute formal equivalency runs using Conformal XL or other industry tools for assigned custom IPs, covering cell behavioralized model versus schematic, and custom IP functional model versus full IP schematic. Set up mappings and constraints and debug non-equivalent points to root cause. Detect and triage RTL-model, schematic-model, primitive, XML, and configuration mismatches early in the development cycle, and work with model owners and design owners to drive them to closure. Investigate and resolve model behavior, hardware-to-software integration, and customer-facing issues escaping into delivery, and feed lessons learned back into tests and coverage. Develop scripts and reusable workflows that improve test generation, regression, audit, traceability, and reporting. Report test status, coverage, equivalence results, and open issues in the team reporting cadence, and document assumptions and limitations. Provide technical guidance, participate in technical reviews, and promote consistent verification practices across the Design Modeling team. Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field. Demonstrated senior-level experience (typically 5 or more years) in digital, custom, analog, FPGA, ASIC, or IP verification, validation, or modeling environments. Strong understanding of digital design fundamentals, RTL concepts, simulation, and the overall design and verification flow. Proficiency in Verilog and SystemVerilog, with working knowledge of UVM a