Process Integration Engineer at Coherent in Jarfalla

  • Company: Coherent
  • Location: Jarfalla, Sweden
  • Job type: full time
  • Workplace: onsite
  • Posted: 2026-10-28

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Job description

Responsibilities: Wafer Process Ownership Own and optimize the integrated wafer fabrication process flow for assigned products. Define and maintain wafer process specifications and control strategies, including MES process flow setup. Analyze process, inline, and test data to understand process behavior and improve yield and manufacturability. Investigate and resolve process deviations and product test failures through systematic root cause analysis. Implement corrective and preventive actions to improve yield, process stability, and product quality. Provide shop floor guidance and support manufacturing teams during process issues. Maintain technical documentation including process specifications, change records, and experimental results. New Product Introduction Design and optimize integrated process flows to enable new products and device concepts. Collaborate with Chip Design and Process Engineering to balance device performance and manufacturability. Plan and manage wafer lots used for prototyping and product development. Characterize integrated processes and evaluate the impact of process and design tolerances on yield and device performance. Support ramp-up and stabilization of new products in manufacturing. Process and Technology Development Development and optimization of new process integration technologies for current and next-generation InP PIC platforms to expand process capability. Plan and execute experiments to develop and optimize process modules. Ensure new integration technologies reach maturity suitable for product process flows. Collaboration Work closely with Chip Design, Process Engineering, Product Engineering, Manufacturing, and Quality teams. Collaborate with global Coherent sites (e.g. Sherman, Fremont, Zürich) Skills & Qualifications: We are looking for candidates with a strong foundation in semiconductor processing, process integration, and device physics. Experience with III-V or photonic device fabrication is highly advantageous but not required. Required MSc or PhD in Engineering Physics, Electrical Engineering, Optoelectronics, or a related field. Hands-on experience working with semiconductor fabrication processes and equipment in a cleanroom environment. Familiarity with semiconductor fabrication processes such as epitaxy, wet etching, plasma etching, thin-film deposition, and photolithography. Experience in semiconductor process integration, process engineering, or related roles in a semiconductor fabrication environment. Experience developing or supporting semiconductor processes from development through product ramp and high-volume manufacturing. Experience with III–V semiconductor or photonic device fabrication is highly advantageous, but candidates with relevant experience from other semiconductor technologies are also encouraged to apply. Technical Skills Strong understanding of semiconductor process integration and interactions between multiple fabrication steps. Ability to analyze manufacturing, inline, and test data to understand process behavior and identify root causes of yield or device performance issues. Experience with statistical methods and tools for process analysis and control (e.g., DOE, FMEA, JMP or similar tools). Experience with process characterization and metrology techniques such as SEM, EDX, electrical measurements, and materials analysis. Experience with CAD layout tools for lithography mask design is beneficial. Knowledge of optoelectronic device physics or III–V device design is a plus. Language Fluent in English. Swedish proficiency is an advantage, with willingness to develop working proficiency. Who You Are Self-driven and naturally curious, with strong motivation to understand underlying process and device interactions and drive technical solutions to completion. Strong analytical and problem-solving skills, with the ability to interpret complex process and test data and identify root causes of yield or device performance issues. Detail-oriented and structured

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