Principal SoC DFT Engineer, HBM at Micron in Folsom, CA

Job description

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an HBM SoC DFT Engineer within the Heterogeneous Integration Group (HIG), you will be responsible for the DFT architecture, implementation, and signoff of complex HBM base-die System-on-Chip (SoC) designs. This role is part of the SoC execution team, working closely with RTL design, verification, physical design, and product engineering to ensure robust, scalable, and manufacturable test solutions from pre-silicon development through tapeout and product bring-up. Responsibilities will include, but are not limited to: Own SoC-level DFT implementation including scan, MBIST, LBIST (as applicable), boundary scan (JTAG), and test access architectures for HBM base-die designs. Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design constraints. Implement and integrate DFT logic at the block, subsystem, and full-chip levels, working closely with RTL and integration teams. Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure. Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff. Work closely with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, and smooth silicon bring-up. Support pre-silicon debug of DFT-related issues and assist with post-silicon bring-up and yield/debug analysis. Partner with CAD and methodology teams to define, improve, and standardize DFT flows across HBM SoC programs. Maintain technical expertise and mentor junior engineers as appropriate. Drive innovation into future HBM generations with a focus on quality, scalability, and manufacturability. Develop Gen-AI driven tools, workflows, and methodologies that leverage Agentic AI. Successful candidates for this position will have: Strong hands-on experience with SoC DFT architecture and implementation. Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts. Familiarity with full RTL-to-GDS SoC flows, including interaction between DFT, synthesis, STA, and physical design. Experience working with large, complex SoCs involving multiple IPs and subsystems. Proficiency with industry-standard EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation. Strong RTL debugging and design analysis skills. Familiarity with scripting languages (Python, Tcl, Perl, etc.) for flow automation. Excellent problem-solving and analytical skills. Strong written and verbal communication skills and the ability to collaborate across global, cross-functional teams. Familiarity with memory systems (DRAM/HBM) and JEDEC specifications is a strong plus. Required Experience Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field. 10+ years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs. Job title and level can scale depending on experience and qualifications. The US base salary range that Micron Technology estimates it could pay for this full-time position is: $199,000.00 - $347,000.00 a year Additional compensation may include benefits, bonuses and equity. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale