Principal Hardware Systems Architect-Compute Platforms at Celestica in San Jose, CA

Job description

Req ID: 140082 Region: Americas Country: USA State/Province: California City: San Jose Summary Celestica is seeking a Principal Hardware Systems Architect for Compute Platforms to provide senior technical leadership for the architecture and development of next-generation AI, accelerated computing, and high-performance data center platforms. This role will lead compute-platform architecture spanning CPUs, GPUs and AI accelerators, memory, storage, PCIe/CXL, scale-up interconnects, and compute-node/tray architecture, while collaborating with peer domain architects and engineering leaders to define complete rack and multi-rack systems incorporating networking, power, thermal, mechanical, firmware, and system-management technologies. This is a system and platform architecture role, not a processor or ASIC design role. The successful candidate will operate above the component level, translating customer requirements, workload needs, and technology roadmaps into scalable compute architectures. A critical aspect of the position is understanding that next-generation AI infrastructure can no longer be optimized as independent compute, networking, power, and cooling subsystems. The Compute Architect will partner closely with Celestica’s Network Architect and other domain experts to optimize the complete AI system from compute node through rack and multi-rack deployments. Skills & Responsibilities: Compute Platform Architecture Define architecture for next-generation AI, accelerated-compute, server, and high-performance computing platforms. Own architectural definition of: CPU architectures GPU and AI accelerator subsystems Memory and HBM architectures PCIe and CXL fabrics Local storage and NVMe architectures GPU/accelerator topology Scale-up interconnect architecture Compute node and tray architecture Establish compute-system requirements, interfaces, partitioning, and architectural tradeoffs. Evaluate alternatives based on performance, bandwidth, latency, power, thermal density, reliability, cost, scalability, serviceability, and manufacturability. Develop reusable compute-platform architectures and building blocks that can be leveraged across customers and programs. AI & Compute Technology Leadership Maintain deep technical understanding of evolving CPU, GPU, AI accelerator, memory, storage, and interconnect technologies. Track and evaluate technology roadmaps from leading compute ecosystem suppliers including NVIDIA, AMD, Intel, ARM ecosystem companies, and emerging AI accelerator providers. Understand emerging AI compute architectures and their implications for: Accelerator density Memory bandwidth PCIe/CXL connectivity Scale-up fabrics Scale-out networking Rack power Liquid cooling Rack and cluster architecture Lead architectural evaluation of scale-up technologies, including NVLink/NVSwitch-class technologies and emerging accelerator interconnects. Integrated Rack & Multi-Rack Architecture Partner with peer system architects to define integrated rack and multi-rack architectures spanning compute, networking, power, thermal, mechanical, firmware, and system-management domains. Optimize architecture as a complete AI system rather than as independent compute or networking platforms. Partner closely with the Network Architect to establish the interface between accelerator scale-up architectures and network scale-out architectures. Jointly evaluate system-level architectural tradeoffs where compute and networking intersect, including: Accelerator density Fabric bandwidth NIC/DPU architecture Switch topology Latency Power consumption Thermal density Reliability Cost Scalability Work with Power, Thermal, Mechanical, Reliability, Firmware, and Validation engineering teams to establish system-level requirements and interfaces. Drive architectural thinking from compute node → tray → rack → multi-rack AI system. Experience Requirements Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Comp