Principal FinFET IC Mask Layout Designer – TeraWave at Blue Origin in San Diego, CA

Job description

Application close date: Applications will be accepted on an ongoing basis until the requisition is closed. At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin is pioneering the future of space-based connectivity with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This network will service tens of thousands of enterprise, data center, and government users who require reliable connectivity for critical operations. Job Description: Blue Origin is seeking candidates with extensive hands-on experience in Analog/mixed-signal IC mask layout in advanced FinFET technologies to participate in and/or lead the physical implementation of high-performance integrated circuits for TeraWave. You will work closely with circuit designers to develop layouts for high-speed data converters (ADCs/DACs), PLLs, filters, amplifiers, clocking, and biasing circuits. You will be responsible for delivering high-quality, manufacturable layouts that meet circuit performance, reliability, and integration requirements, while contributing to innovative solutions that drive Blue Origin’s mission of enabling millions to live and work in space for the benefit of Earth. Responsibilities and technical leadership scope will vary according to experience and level. Special Mentions: - Relocation provided - Travel expected up to 10% of the time - Interviews will include a technical assessment - This role is based on site in San Diego (preferred), CA; or Cupertino, CA. A temporary remote work exception is approved while our San Diego site is being developed. Responsibilities include but are not limited to: Develop custom transistor-level layouts for analog/mixed-signal circuits in advanced FinFET technologies, including floorplanning, top level integration, device placement, routing, and physical verification. Collaborate with circuit designers to meet performance, matching, noise isolation, area, and reliability requirements. Apply FinFET-specific layout techniques to address device geometry constraints, orientation, layout-dependent effects, and parasitic coupling. Implement matched device structures, sensitive signal routing, shielding, and isolation appropriate to circuit requirements. Perform design rule checking (DRC), electrical rule checking (ERC), and layout-versus-schematic (LVS) verification; investigate and resolve complex verification errors. Generate parasitic extraction results and collaborate with circuit designers to identify and resolve layout-related performance issues. Implement power and ground distribution that meets electromigration, current density, and voltage-drop requirements. Develop layout schedules, identify implementation risks and dependencies, and deliver verified layouts in alignment with project milestones. Support hierarchical planning, top-level integration, and tape-out preparation, including ESD structures, pad integration, density fill, and applicable design-for-manufacturability checks. Collaborate with circuit designers, CAD engineers, and foundry partners to resolve layout, PDK, and verification issues. Lead layout reviews, document best practices, and mentor less-experienced layout designers. Minimum Qualifications: Bachelor’s degree in electrical engineering 10+ years of relevant professional experience Understanding of basic electrical parameters and relationships such as Ohm’s law, performing calculations for sizing metal layers to meet IR drop requirements and current density, etc. Direct hands-on experience developing analog/mixed-signal custom layouts in FinFET technologies. Strong understanding of device matching, symmetry, parasitic effects, noise i